1. Field of the Invention
The present invention relates to a method for treating a wafer, and more particularly, to a method for treating a wafer to protect a fuse box of a semiconductor chip, thereby preventing the degradation of the semiconductor chip.
2. Description of the Related Art
During the manufacture of semiconductor chips, redundancy memory cells are formed in each sub-array block. For instance, cells corresponding to redundant rows and columns are formed in each 256 K cell array. After the fabrication of semiconductor chips is completed, a wafer-level electrical test is performed thereon to sort out the defective semiconductor chips. Then, good semiconductor chips are selected, assembled, and packaged. The defective chips that are detected during the electrical test, however, can be repaired through a repair process. In the repair process, a defective memory cell is replaced with a redundancy memory cell. This is realized by cutting a proper fuse so that the selected line of a defective memory cell is replaced with the line of a redundancy cell when an address signal corresponding to the line of the defective memory cell is input during the later use of a semiconductor chip. An excessive current and laser beam is typically used in cutting the fuse. In particular, the use of a laser beam is preferred because it is simple and reliable and easy to lay out the fuse.
A semiconductor chip includes a variety of fuses, including fuses used during the repair process, e.g., a fuse for trimming the level of a DC generator, a fuse for selecting a chip, and an oscillator fuse. A region occupied by these fuses is referred to as a ‘fuse box’ and described with respect to its schematic structure while referring to FIGS. 1 and 2.
FIG. 1 is a plan view of a general fuse box 100. As shown in FIG. 1, the fuse box 100 is placed on a wafer W and may include a plurality of fuses 10. Each fuse 10 is arranged in the vertical direction. The fuse box 100 of FIG. 1 is a rectangular-shaped fuse box having seven fuses 10. Reference numeral ‘50’ denotes a blocking layer that prevents moisture from permeating through a cell array (not shown) from the fuse box 100.
FIG. 2 is a cross-sectional view of the fuse box 100 of FIG. 1, taken along line II-II′. Referring to FIG. 2, the blocking layer 50 is a multi-layered structure in which metal lines 25 and 35 are formed between insulating layers 20 and 30 and between the insulating layer 30 and a passivation layer 40, respectively.
In general, once the fabrication of a semiconductor chip is completed, a passivation layer such as polyimide is formed on a wafer to protect the semiconductor chip, prior to a wafer-level electrical test. However, a passivation layer that covers a contact pad and a fuse box need to be removed to expose the contact pad and the fuse box, for example, during the wafer-level electrical test in which an electrical signal is applied onto the contact pad, and during the repair process in which a fuse is cut.
Although the fuse box 100 of FIG. 1 has the blocking layer 50, it is not possible to sufficiently prevent the cell array from being moistened when a void occurs in the metal lines 25 and 35. As the semiconductor chip is being manufactured, a native oxide layer may be formed on the surface of an exposed fuse. The oxide layer is prone to being formed at irregular intervals or formed incompletely, and, thus, is not capable of preventing moisture permeating through the fuse box.
Furthermore, unlike the cell region covered with a passivation layer, a fuse box is not protected with a passivation layer. Thus, the fuse box is vulnerable to a high-temperature atmosphere and impurities such as dust, which can lead to the malfunction of a particular chip. For example, if moisture gets into the fuse box, a fuse in the fuse box is eroded. Also, if the fuse box is exposed to the high-temperature atmosphere, the volume of the fuse box expands, causing a crack in the fuse box. When assembling a multi-chip, a crack in the fuse box may cause the chip to be damaged or degraded if a physical stress is applied onto the chip. Also, short circuit may occur if impurities undesirably enter into the fuse box.
Accordingly, there is a need for overcoming these problems to improve the lifetime and reliability of highly-integrated semiconductor circuit chips.